The present invention relates to piezotronics, and more specifically, to piezoelectronic devices with force amplification designs.
Piezotronics is a new field of computer technology based on the piezoelectronic transistor (PET) and variants. In PET operation, a piezoelectric (PE) layer, that expands or contracts with an applied voltage, is used to compress a piezoresistive (PR) layer that changes its resistivity upon pressurization. When the PR layer is non-hysteretic, compression and decompression act as a switch that opens and closes a conductive channel. Three and four terminal switches have been described in the prior art (U.S. Pat. No. 7,848,135; U.S. Pat. No. 8,159,854; U.S. Pat. No. 8,247,947; and U.S. Patent Publication No. 2013/0009668 A1), along with new designs for logic that use these switches.
When the PR layer is hysteretic, a period of high compression followed by a partial release can set the resistance to a low and stable value, and a period of low compression and release can set the resistance to a high and stable value. Such a device makes a piezoelectronic memory (PEM) cell. PEM using hysteric phase change material has been proposed in the prior art (ELMEGREEN et al., U.S. patent application Ser. No. 13/719,965).
A four-terminal PET from the prior art is shown in FIG. 1 for reference. The viewpoint is from the side and fabrication is in layers from the bottom to the top. Two gate electrodes actuate the PE layer, which expands and contracts vertically (the z direction) according to the voltage drop across them. Two sense electrodes straddle the PR layer and sense the resistance across it. These two pairs of electrodes are separated from each other by an insulator. The current through the PR layer is along the axis of the device, the same direction as the applied field on the PE layer.
A thinner PR layer is advantageous because its internal pressure can be increased to the required switching pressure with a smaller expansion of the PE layer. However a potential disadvantage of the design in the prior art is that the thickness of the PR layer is limited to a few nanometers by quantum tunneling. Smaller dimensions are likely to have undesirable leakage currents from quantum tunneling through the PR layer. Quantum tunneling is also a problem for conventional CMOS FETs.
The present invention proposes solutions to the limitations that are inherent in the prior art.